1. Field of the Invention
This invention relates to semiconductor devices, and more particularly to a semiconductor device in which the generation of cracks caused by thermal stress is suppressed in the outer peripheral area of a semiconductor chip.
2. Description of the Related Art
There has been used a resin-molded semiconductor device wherein a semiconductor chip whose surface is covered with a passivation film is sealed with a resin. In the semiconductor device of this type, since the coefficients of thermal expansion of the semiconductor chip and the sealing resin are different, cracks generated in the passivation film by thermal stress may have harmful effects.
Therefore, a method according to which dummy interconnects are formed in the inner pattern region of the semiconductor chip has been proposed with the intention of suppressing the generation of the cracks in the passivation film caused by the thermal stress.
In general, as shown in FIG. 3, the surface of a semiconductor chip includes an inner pattern region 20 which has functional elements such as transistors, interconnects, etc., a region 22 which surrounds the inner pattern region 20 and in which a plurality of bonding pads 21 are arranged, and a reserved region 23 which extends from the outer periphery of the region 22 having the bonding pads 21 arranged therein to the outer periphery of the chip. Each of the bonding pads 21 is, for example, in a rectangular shape whose side is about 100 xcexcm. Besides, the reserved region 23 is a region disposed in order that cracks, which arise from a scribed surface in dicing a semiconductor wafer every chip, may be prevented from reaching the inner pattern region 20 which includes the functional elements. Usually, the reserved region 23 is formed with quite no pattern for functioning in a semiconductor device. More specifically, as shown in FIG. 4, a first interlayer insulating film 24, an SiN film 25 formed by plasma CVD method, an SOG (spin-on-glass) film 26, SiO2 films 27, 28 formed by plasma CVD method, and a passivation film 29 are successively stacked in the reserved region which is located at the outer peripheral part of the semiconductor chip, and they are overlaid with a sealing resin 30.
Usually, the semiconductor device is so constructed that a plurality of wiring layers and interlayer insulating films are stacked as a multilayer wiring structure. Therefore, in order to prevent the damege to the overlying wiring layers, etc. from occurring due to the unevenness of a wafer surface, an SOG film having a flattening effect as the interlayer insulating film is employed in combination with insulating films which are formed by CVD method. The SOG film is formed in such a way that a solution, which is obtained by dissolving an organic silane-based source material in a solvent, is applied onto the wafer surface by spin coating and is heated.
However, when such a semiconductor device is subjected to temperature cycle tests in a temperature range of 150xc2x0 C. to xe2x88x9265xc2x0 C. about 500 to 1000 times by way of example, the SOG film 26 peels off at its interfaces with the SiN film 25 and the SiO2 film 27 formed under and over it by the CVD method, as shown in FIG. 5. As a result, cracks may be generated in the SOG film 26.
A semiconductor device to cope with the above drawback has been proposed in, for example, Japanese Patent Application Laid-open HEI 8(1996)-306771. More specifically, as shown in FIG. 6, in the reserved region of a semiconductor chip, an interlayer insulating film 31 is overlaid with a plurality of first dummy interconnects 32, an interlayer insulating film which consists of an SiN film 33, an SOG film 34 and an SiO2 film 35, and second dummy interconnects 36 which are buried in dummy via holes formed in the interlayer insulating film and which are arranged over the dummy via holes. Further, the resulting structure is covered with an SiO2 film 37 and a passivation film 38.
Owing to such a construction, the residual area of the SOG film 34 is, in effect, decreased so as to prevent the SOG film 34 from peeling off the SiN film 33 as well as the SiO2 film 35 and from cracking due to the peeling.
The semiconductor device of the above construction, however, involves the problem that, when the first and second dummy interconnects 32, 36 are patterned in fine or small shapes, it is difficult to prevent the peeling of the interlayer insulating film and the generation of the cracks. Another problem is that steps at the surface of the passivation film 38 enlarge due to the formation of the first and second dummy interconnects 32, 36, so a filler contained in a sealing resin is liable to enter the recess between these interconnects, resulting in the generation of cracks in the passivation film 38 and also in the interconnects 32, 36 themselves. A further problem is that, with some methods for patterning the first and second dummy interconnects 32, 36, stress concentrates in the corner area of the semiconductor chip, causing the generation of cracks in this corner area.
The present invention provides with a semiconductor device comprising a first dummy interconnect, an interlayer insulating film and a second dummy interconnect which are formed on a semiconductor chip in this order and a plurality of dummy via holes formed in the interlayer insulating film between the first dummy interconnect and the second dummy interconnect; wherein at least one of the first dummy interconnect and the second dummy interconnect is connected with at least two of the dummy via holes.